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The knowledge and intelligence you need to be |
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Always on target |
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Specification summary: |
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Analog Signal Inputs |
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Number of input channels: |
2 independent |
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AD converter type: |
AD 9245 |
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Bit: |
14 |
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Sampling rate: |
80MSPS |
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Analogue input bandwidth: |
320MHz |
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Analog Signal Outputs |
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Number of output channels: |
2 independent |
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DA converter type: |
AD 9744 |
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Bit: |
14 |
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Sampling rate: |
80MSPS |
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Analogue output bandwidth: |
160 MHz |
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Data buffering |
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Type of buffer: |
FIFO |
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Size of FIFO: |
262 Kword (1 word=16 bits) |
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Digital interfaces |
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FPGA: |
Xilinx Virtex II |
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PCI chip: |
PLX PCI 9656 |
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DMA: |
Master enabled, via the PCI chip |
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Direct data port for DSP: |
Optional |
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Clock distribution |
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External clock: |
Via front panel connector. |
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Type: |
Sine wave +4 dBm - +10 dBm |
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Ratio: |
1x, 2x, 4x, 8x, 16x (manufacturing option) |

Features
Industry Standard PCI Form Factor
4 Independent Analog to Digital Converters
4 Digital Down Converters with 16 Channels
320 MHz Analog Input Bandwidth
Up to 80MSPS Sampling Rate
Up to 90dB Linear Dynamic Range
Typical Applications
Multi-mode Software Defined Radio Receiver
Multi-channel Narrowband Digital Receivers
Beamforming (smart antenna)
Interferometer Radio Direction Finding
Signal Intelligence (SIGINT) Capturing
Product description
DRU-304A is a multifunctional analog input card with 4 ADC channels. The output
data stream of ADCs is processed by digital down converter (DDC) chips (AD6624),
which are able to tune their 16 digital channels anywhere into the frequency
pass band and down convert the signal to a base band domain. The 16 out channels
of the down converters fed into the FPGA for further processing. From the FPGA
it is possible to forward the data through the PCI bus or using the dedicated IO
ports directly to a DSP unit. The down converters could be programmed through
PCI.
This multifunctional receiver board combines high-speed analog to digital
conversion with digital processing suitable for multi channel
wide-and/narrow-band/phase-array down conversion and filtering.
Functional block diagram

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Specification summary: |
|
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Analog Signal Inputs |
|
|
Number of input channels: |
Up to 4 independent |
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AD converter type: |
AD 9245 |
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Bit: |
14 |
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Sampling rate: |
80 MSPS |
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Analogue input bandwidth: |
320MHz |
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Receiver |
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Down converter: |
AD6624 four-channel digital receiver chip. |
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Number of down-converters on the board: |
4 |
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Number of receiver channels: |
16 |
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Max. bandwidth: |
1 MSPS |
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Decimation ratio: |
16 -16384 |
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Digital interfaces |
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FPGA: |
Xilinx Virtex II |
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PCI chip: |
PLX PCI 9656 |
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DMA: |
Master enabled, via the PCI chip |
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Direct data port for DSP: |
Optional |
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Clock distribution |
|
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External clock: |
Via front panel connector. |
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Type: |
Sine wave +4 dBm - +10 dBm |
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Ratio: |
1x, 2x, 4x, 8x, 16x (manufacturing option) |








© 2012 Sagax, Ltd.
Sagax, Ltd. Raday u. 33/B. Budapest, 1092 Hungary, TEL: +36-1-219-5455, FAX: +36-1-219-5456